1. Field of the Invention
The invention relates to a wiring structure of data lines in a semiconductor integrated circuit.
2. Description of the Related Art
Conventionally, a semiconductor integrated circuit, such as a DRAM, includes shield wires each interposed between data lines so as to avoid coupling noise from their adjacent wires. However, when the number of data bits is large, the required number of data lines becomes large, and hence the number of the shield wires accordingly increases. As a result, the wiring region of the data lines is disadvantageously enlarged. Japanese Unexamined Patent Application Publication No. 2001-23374 discloses a technique that in a DRAM, the write and read data lines which are not simultaneously used for transferring data are alternately wired and that the write data lines are utilized as shield wires during the read operation, while the read data lines are utilized as shield wires during the write operation. This wiring structure requiring substantially no shield wires prevents an increase in the wiring area.
FIG. 1 shows a wiring structure of data lines for transferring data between memory cell arrays and a data input/output circuit in a semiconductor integrated circuit as described above. Between the memory cell arrays and the data input/output circuit, there are alternately wired write data lines WDL and /WDL for transferring complementary write data during the write operation and read data lines RDL and /RDL for transferring complementary read data during the read operation. These write and read data lines WDL, /WDL, RDL and /RDL are wired by use of the same wire pitch as, for example, complementary bit lines BL and /BL (bit line pairs) (not shown). That is, the write data lines WDL and /WDL and the read data lines RDL and /RDL are wired corresponding to the respective bit line pairs in the memory cell arrays and are shared between these bit line pairs.
As shown in FIG. 1, there exist parasitic capacitances C0 between the adjacent data lines. There also exist parasitic capacitances C1 and C2 between the data lines and the semiconductor substrate and between the data lines and a metal wire UL of the overlying layer, respectively. Since every data line has a total parasitic capacitance of xe2x80x9c2C0+C1+C2xe2x80x9d, the data transfer times (delay times) necessary for transferring the data along the respective data lines are equal.
In a semiconductor integrated circuit such as a system LSI including a DRAM core, data read from the DRAM core may be directly outputted to a controller in the integrated circuit, and data to be written into the DRAM core may be directly inputted from the controller. In the above semiconductor integrated circuit, simultaneously outputting to the controller many pieces of data read from the memory cells onto the bit lines and then amplified by the sense amplifiers can improve the data transfer rate. In this case, since the data lines cannot be shared between bit line pairs, the data lines must be formed corresponding to each bit line pair. For this reason, unlike FIG. 1, a plurality of wiring layers must be used to form the data lines.
FIG. 2 shows an example wherein two wiring layers L1 and L2 are used to wire the data lines. In this example, the write and read data lines WDL and /RDL are alternately wired in the wiring layer L1 overlying the semiconductor substrate, and the read and write data lines RDL and /WDL are alternately wired in the wiring layer L2 overlying the wiring layer L1. Using these two wiring layers L1 and L2 allows the write data lines WDL and /WDL and the read data lines RDL and /RDL to be wired corresponding to each bit line pair. For this reason, many pieces of data amplified by the sense amplifiers can be simultaneously outputted to the controller or the like via the write and read data lines WDL, /WDL, RDL and /RDL. This can improve the. data transfer rate.
In the wiring structure of FIG. 2, however, parasitic capacitances C0 and C3 exist between the adjacent data lines in the wiring layer L1 and between the adjacent data lines in the wiring layer L2, respectively. Parasitic capacitances C1 and C2 also exist between the data lines of the wiring layer L1 and the substrate and between the data lines of the wiring layer L1 and the data lines of the wiring layer L2, respectively. Parasitic capacitances C4 also exist between the data lines of the wiring layer L2 and the metal wire UL of the overlying layer. As a result, in FIG. 2, every data line of the wiring layer L1 has a total parasitic capacitance of xe2x80x9c2C0+C1+C2xe2x80x9d, while every data line of the wiring layer L2 has a total parasitic capacitance of xe2x80x9c2C3+C2+C4xe2x80x9d.
In the wiring structure of FIG. 2, since the parasitic capacitances associated with the data lines are different between the wiring layers L1 and L2, the data transfer times (delay times) necessary for transferring the data along the data lines of the wiring layers L1 and L2 are also different. In many cases, the insulator film formed on the semiconductor substrate is different in material and thickness from the insulator film formed under the metal wire UL. For this reason, the difference especially between the capacitances C1 and C4 is large. The parasitic capacitance difference results not only from the materials of the insulator films but also from the tolerance of the fabrication process.
Thus, there is a possibility that complementary write data transferred along the data lines WDL and /WDL cannot be transferred to the memory cell array at the same timing, resulting in an erroneous data write into the memory cells. Similarly, there is also a possibility that complementary read data transferred along the data lines RDL and /RDL cannot be transferred to the controller or the like at the same timing, resulting in incorrectly reading the data read from the memory cells.
It is an object of the present invention to prevent the circuit malfunction which would otherwise occur due to a parasitic capacitance difference, by equalizing the parasitic capacitances associated with the data lines in a semiconductor integrated circuit that uses a plurality of wiring layers to transfer data. In particular, it is an object of the present invention to prevent the circuit malfunction by equalizing the data transfer times when complementary data lines are used to transfer data.
According to one of the aspects of the semiconductor integrated circuit of the present invention, in the first region, a first data line is wired by use of a first wiring layer formed over a semiconductor substrate, and a second data line extending over the first data line is wired by use of a second wiring layer formed over the first wiring layer. In the second region, the second data line is wired by use of the first wiring layer, and the first data line extending over the second data line is wired by use of the second wiring layer. Here, data is transferred to the first and second data lines at respective different timings.
A switching region is formed between the first and second regions. In the switching region, the first data line wired in the first region is connected to the first data line wired in the second region, and the second data line wired in the first region is connected to the second data line wired in the second region. In the switching region, at least either of the first data lines and the second data lines are connected to each other via a third wiring layer formed over the semiconductor substrate.
In general, the parasitic capacitances formed between the data lines formed in the first wiring layer and the semiconductor substrate are different from the parasitic capacitances formed between the data lines formed in the second-wiring layer and its overlying wire. According to the present invention, vertically reversing positioning of the first and second data lines between the first and second regions substantially equalizes the total parasitic capacitances associated with the first data lines and the second data lines. This results in equalizing the delay times of the signals transferred along the first and second data lines, thereby preventing the circuit malfunction which otherwise would occur due to a parasitic capacitance difference.
Moreover, this vertically reversed positioning of the first data lines and second data lines between the first and second regions makes it possible to shorten the distances at which the first and second data lines extend in parallel to the overlying or underlying wires. This can prevent the circuit malfunction which otherwise would occur due to coupling capacitances caused between their adjacent wires.
According to another aspect of the semiconductor integrated circuit of the present invention, a memory core is composed of having alternately arranged memory cell arrays each having a plurality of memory cells and sense amplifier arrays each having a plurality of sense amplifiers. The first and second regions are alternately formed over the memory cell arrays, and the switching regions are formed over the sense amplifier arrays. The first data lines transfer write data to be inputted to the memory cell arrays at a write operation, and the second data lines transfer read data outputted from the memory cell arrays at a read operation. The write and read data are inputted to/outputted from the memory cell arrays via the sense amplifiers, respectively.
In general, the read data are amplified by the sense amplifiers and then outputted to the data lines during the read operation of the memory core. During the write operation of the memory core, the write data transferred to the data lines are amplified by the sense amplifiers and thereafter written into the memory cells. That is, the first and second data lines for transferring the write and read data respectively, are both connected to the sense amplifiers. For example, the first and second data lines are connected to the sense amplifiers via different wiring layers and through-holes over the sense amplifier arrays. Since the first and second data lines are formed over the sense amplifier arrays by use of a plurality of wiring layers, the formation of the switching regions over the sense amplifier arrays can facilitate the connection of the first and second data lines of the first region to the first and second data lines of the second region.
The sense amplifier arrays have a lower density arrangement of elements such as transistors than the memory cell arrays. The formation of the switching regions over the sense amplifier arrays having such a lower element arrangement density also can facilitate the connection of the first and second data lines to the memory cell arrays.
According to another aspect of the semiconductor integrated circuit of the present invention, the first data lines are fixed at a first voltage during the read operation, and the second data lines are fixed at the first voltage or a voltage different from the first voltage during the write operation. That is, the first data lines serve as shield wires during the read operation, while the second data lines serve as shield wires during the write operation. When either the first data lines or the second data lines transfer data, the other data lines serve as the shield wires. This can prevent the coupling noise from their adjacent wires and hence prevent the circuit malfunction.
According to another aspect of the semiconductor integrated circuit of the present invention, in each of data line regions, the first and second regions are alternately arranged in the alignment direction of the memory cell arrays. In other words, one data line region composed of first and second data lines is formed adjacent to another data line region composed of another first and second data lines. In adjacent data line regions over a single memory cell array, the first and second regions are adjacent to each other. That is, the positioning of the first and second regions is vertically reversed between two adjacent data line regions. Two pieces each of write and read data to be transferred to the two data line regions may be complementary or may be of single phase. Having the wiring structure as described above prevents the concurrent operations of not only vertically adjacent data lines but also horizontally adjacent data lines. This can further prevent the coupling noise which otherwise would occur from vertically and horizontally adjacent wires.
According to another aspect of the semiconductor integrated circuit of the present invention, the memory cells are connected to the sense amplifiers via any bit line of complementary bit line pairs. Two data line regions where the complementary write data and the complementary read data are transferred are formed corresponding to the bit line pair. That is, each of the two data line regions is formed corresponding to the respective bit lines of each of a plurality of bit line pairs. For this reason, all the data read from the memory cells and then amplified by the sense amplifiers can be outputted to the exterior of the memory via the data line regions at the same time. Also, all the write data inputted from the exterior through the data line regions and then amplified by the sense amplifiers can be written into the memory cells at the same time. This can improve the transfer rates of the read and write data.